1. Field of the Invention
The present invention relates to the integration of passive elements into a silicon carrier structure for connecting integrated circuits, components, and other semiconductor components.
2. Brief Description of Related Developments
In advanced electronic computing systems the decoupling capacitors serve as a charge reservoir to support instantaneous current surges that invariably accompany simultaneous circuit switching. They are employed on chip and across all levels of packaging, including single chip and multi chip modules, board and back plane. In addition these passive components are required in the power distribution systems for integrated circuits (IC) to reduce the simultaneous circuit switching noise, or ΔI (Delta I) noise. However, the ability to support an adequate decoupling capacitance at high frequencies is of increasing concern in both on-chip and off-chip systems. The relentless scaling to ever smaller device dimensions and faster circuit speed at the chip level have driven the demand for higher packaging density, but they also drive a need for new solutions to the increasing decoupling dilemma.
In particular, the decoupling capacitors have to not only possess sufficient capacitance, but also must be accessible in time scales comparable to the ever shorter clock cycle times, resulting from increasing circuit speeds. The increase in power efficiency required in microprocessor units, especially for portable computing and communication needs, has further exacerbated the problem. A proposed solution is clock gating (the ability to turn off clock circuits in unused parts of the chip); however, this increases the number of switching events dramatically and brings new complications because of greatly increased I noise. In order to achieve a desired damping of the voltage fluctuations associated with the ΔI noise, damping resistive elements also may need to be incorporated along with the decoupling capacitive elements. Hence, new solutions that address all of these issues and allow for more effective integration of various capacitive and resistive components in close proximity to the processor circuitry are needed. In one solution, decoupling capacitance is incorporated into the substrate of a chip, as described in commonly owned U.S. Pat. No. 5,811,868.
Currently used passive decoupling elements are generally based on thin or thick film ceramic technology, thin film on silicon, or several small discrete surface mounted devices built into one large package. In the case of electronic package applications, currently used discrete capacitors do not have sufficiently low enough parasitic inductance to be used in the high frequency or high speed circuits being proposed for the near future. The ability to bury passive devices (integrated passives [IPs]) within printed wiring board or modules opens up space for mounting other components that now can be placed where previously discrete passive components were located. The thin film-based IP devices exhibit better high frequency performance and provide easier component integration schemes. These components must be fabricated using technology compatible with carrier materials and fabrication processes. In addition, to meet future high performance needs, the decoupling elements must be electrically accessible within a time frame comparable to the clock cycle times of device chips.
Building these elements on the processor chip would provide an acceptable access time but this would take up chip real estate away from active circuits that need to be built on these high performance chips. It is therefore clear that a better solution is needed to provide decoupling capacitors and resistors with appropriate properties, and to place them where they are accessible to the device circuitry on the chips within a time close to the chip clock cycle.